1. Field of the Invention
The present invention relates to a method for forming silicon oxide, which is used in, for example, an interlayer insulator of a semiconductor device.
2. Description of the Related Art
The use of a multi-level interconnection is increased if degree of integration of the element constituting an LSI is increased.
The reason is as follows:
If the size of the element is reduced and the number of elements to be formed in one LSI is increased, the interconnection becomes complex and large-scaled. On the other hand, the size of the wire constituting the interconnection and the pitch cannot be made small.
The interlayer insulator is needed in a case where the semiconductor device using the multi-level interconnection is formed.
Conventionally, the interlayer insulator is formed by plasma CVD.
In a case where the interlayer insulator is formed of silicon oxide, a main gas includes TEOS (tetraethyl orthosilicate, which is expressed by Si (OC.sub.2 H.sub.5).sub.4) and oxygen (O.sub.2) in plasma CVD.
Moreover, in plasma CVD, for improving a step coverage of silicon oxide to the wire, gas for etching silicon oxide, that is, gas of NF.sub.3 is added to the main gas.
However, even if gas of NF.sub.3 is added to the main gas, a space between a wire 11A and a wire 11B cannot be completely filled with a silicon oxide 12 when a ratio of a width W between the wires 11A and 11B to a height H of the wire, i.e., aspect ratio (H/W) is 1 or more. Due to this, a void 13 is generated between the wires 11A and 11B.
The generation of the void 13 makes reliability of the semiconductor device worse.
In order to solve this problem, there has been proposed a method in which the space between the wires 11A and 11b is filled with silicon oxide 12 without generating the void 13.
The above-mentioned method is plasma CVD in which two high frequencies, i.e., high frequency of 13.58 MHz and high frequency of several hundreds kHz are used to generate plasma.
According to the above method, the space between the wires can be completely filled with silicon oxide even if the aspect ratio (H/W) is 1 or more.
Moreover, according to the above method, the larger an element ratio of silicon (Si) to fluorine (F) (F/Si) becomes, the better the step coverage of silicon oxide to the wire becomes.
However, there is a problem in the point that, for example, as the larger the element ratio of silicon (Si) to fluorine (F) (F/Si) becomes, the more a characteristic of a gate insulating film of an MOS transistor is deteriorated.
Moreover, as the larger the element ratio of silicon (Si) to fluorine (F) (F/Si) becomes, the higher concentration of fluorine (F) of silicon oxide to be formed by plasma CVD becomes. If the concentration of fluorine (F) of silicon oxide to be formed by plasma CVD becomes higher, silicon oxide easily absorbs moisture. In other word, there is a problem in the point that moisture absorption of silicon oxide is increased and a characteristic of silicon oxide is deteriorated.